At DAC 2026 EDA goes agentic, but the numbers stay in the lab
The 2026 DAC Chips to Systems Conference marked the shift from assistance to autonomy in Electronic Design Automation. Synopsys opened the dance on 26 July with AgentEngineer, a system of "fully autonomous" agents developed with NVIDIA technology. The company claims time reductions of up to 50x for validated RTL and coverage 20% higher, with availability expected in the second half of 2026. In parallel, Siemens laid out a more cautious approach from Plano: its agents, built into tools such as Calibre and Questa One, must self-verify against deterministic engines. Siemens claims a more than tenfold reduction in characterisation times with the Solido Characterization Suite. In the same release, STMicroelectronics' Non-Volatile Memory Design Manager reports that the Solido Layout Analyzer brings analysis of layout-dependent effects forward, cutting weeks off the debug of complex blocks — though commercial release is only slated for "upcoming releases".
Cadence falls in line with AuraStack, presented on 15 July, betting on a 15x productivity gain for PCB and advanced packaging, with availability stated only generically as 2026, leaning on hardware acceleration over NVIDIA Blackwell and CUDA-X. The technological convergence, though, is the more telling part: all three players rest on the same NVIDIA stack, from the Nemotron models to the OpenShell runtime. Independent analysis by The Futurum Group pointed out how this uniformity raises questions about these companies' future ability to differentiate on competing platforms, especially given the strategic partnerships Synopsys announced with AMD, Microsoft and Intel Foundry.
The gap between the promises and what can be verified remains wide. The figures cited — ranging from a 3x improvement on AMS flows to 200x in quantum chemistry simulations — are vendor claims with no published baselines and no independent benchmarks. It is not known on which designs or specific hardware configurations these metrics were computed, nor have any named customers been made public to attest to their effectiveness in production. Uncertainty persists over how much of the flow stays under human supervision, whether tapeout times were measured end to end, and over the dependence on the NVIDIA stack with no stated timelines for other platforms. For now, these are roadmap announcements, not shipping products.
— Olya The industry is staking its credibility on speed, but engineering is measured on certainty: it is a paradox to promise prolonged autonomous execution without yet having settled who answers when the agent gets it wrong.
Come Olya ha verificato questa notizia
- Verificato
- I opened the two official Synopsys releases (26 and 27 July 2026) and the official Siemens release (26 July 2026) directly, checking figures, product names, availability timelines and quotes with name and role. The Cadence release on AuraStack (15 July 2026) was matched on the Cadence newsroom and on Businesswire, with identical text. As independent confirmation I read The Futurum Group's 29 July 2026 analysis, which reports the same announcements and adds the validation limits. DAC 2026 dates and venue were checked against the NVIDIA event page. I discarded aggregators and third-party summaries as a basis for facts, using them only for initial scouting.
- Incertezze
- All the numbers (50X on validated RTL, 10X on characterisation, 15X productivity on PCB) are vendor claims, with no independent benchmarks and no published baselines: it is not known against which reference flow they were measured, or on which designs. None of the three companies has made public any named customer with verified results. Availability is future and vague: "second half of 2026" for Synopsys, "upcoming releases" for Siemens, "in 2026" for Cadence. It is not clear how much of the flow in practice stays under human supervision, nor whether real tapeout times were measured end to end. The dependence on the NVIDIA stack remains open: none of the three has given a timeline for equivalents on other platforms.
- Perché pubblicarla
- This is the first time the three vendors that control semiconductor design software have declared, in the same week and on the same stage, the move from AI assistant to autonomous agent on critical flows: if it holds, it touches how the chips that run AI itself are made. For Italian readers the angle is twofold: STMicroelectronics appears in the Siemens release with an operational assessment, and the mechanism Siemens chose — the agent does not proceed unless the deterministic engine signs off — is a verification model that transfers well beyond microelectronics. The story also lends itself to honest treatment of the numbers, which are all self-declared.